Technical Staff Engineer-Design Jobs

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Microchip’s Data Center Solutions (DCS) Business Unit offers industry leading performance, reliability, and security for PCIe Switches, and NVME Controllers. As a Principal Engineer-Design, you will provide leadership in the highly successful PCIe Switch product line. These complex 200M gate+ integrated silicon devices enable top tier data centers in next gen storage, artificial intelligence and automotive market segments.
As a Principal Engineer-Design , your job will entail the following:

• Define subsystem/block feature sets, describe design and implementation details into engineering documents and registers documents
• Read and understand applicable storage and computer interface protocol standards
• Design of complex digital integrated circuits at the block, subsystem or device level (100K to 50M+ gates), which are coded in Verilog, System Verilog
• Support emulation, ASIC lab validation including lab debug and providing logic modifications and workarounds
• Communicate regularly with the design and verification team in multiple locations to resolve issues, communicate status and solve technical problems
• Communicate with architects to justify design implementation decisions and associated trade-offs

Requirements/Qualifications

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering or equivalent
• Experience with Formal Verification a plus.
• Excellent knowledge in logic synthesis and static timing analysis.
• Capable of debugging EDA tool issues or design related issues.
• Protocol knowledge and experience in PCI-Express will be an asset
• Scripting and programming skills using csh, bash, perl, python, tcl, etc.
• Working knowledge of design and verification tools such as Synopsys Design Compiler, Cadence Incisive, waveform viewers, and other similar tools.
• Experience in designing the chip top level with IOs, pin out and package design
• Working knowledge of DFT.
• Good verbal and written communication skills in English will be an asset
• Excellent analytical and debugging skills and the ability to proactively solve issues
• Worked with physical design teams for layout implementation. Familiar with low power methodology and flows.
• Excellent teamwork and time management skills, self-direction, the ability to work under pressure and the desire to excel in a competitive environment
• RTL Design - Experience in RTL Design using System Verilog, Verilog is required.
• Experience and understanding of complex ASIC design flows, including block and chip level simulation and debug, logic synthesis, static timing analysis, layout and revision control
• 8+ years related experience
• Knowledge of AHB/AXI bus protocols is desired.

Travel Time
0% - 25%