Senior Digital Verification Engineer

Ciena is committed to our people-first philosophy. Our teams enjoy a culture focused on prioritizing a personalized and flexible work environment that empowers an individual’s passions, growth, wellbeing and belonging. We’re a technology company that leads with our humanity—driving our business priorities alongside meaningful social, community, and societal impact.
Why Ciena

• Our team supports an inclusive, diverse and barrier-free work environment making for empowered and committed employees.
• You will be a member of a successful team working on the forefront of technological innovation focused on leading edge technologies, flows and products. You will be working with, and learning from, industry recognized experts.
• Great work deserves recognition. We have a robust recognition program, with ongoing and enhanced awards for exemplary performance.
• We recognize the importance of well-being and offer programs and benefits to support and sustain the mental and physical health of our employees and their families.

How You Will Contribute
The Wavelogic family of products are widely used in Ciena's optical fiber transmission solutions, and are one of the main contributors to Ciena's success in the telecommunications industry. Reporting to Senior Manager, as a Senior Digital Verification Engineer, in conjunction with a team of Digital Design Engineers, Verification Engineers and Architects, you’ll play a key role in implementing innovative verification strategies, in order to thoroughly simulate and validate functional blocks and subsystems for the Wavelogic family of products.

• You will be responsible for completing and thorough validation of one or more architectural functional blocks by using an appropriate combination of simulation, formal and coverage methods.
• You will create the verification, functional coverage and formal verification test plans
• You will be accountable for the creation of testbench environment and/or components, agents, scoreboard, and all test scenarios related to your architectural functional block using System Verilog UVM and/or C, where applicable.
• You will perform coverage driven verification, monitor regressions and debug resulting failures with the help of the function's designer and provide status updates on a regular basis.
• You will read and understand the architecture and functional requirements specification document(s) and communicate and collaborate with systems engineers and architects.

What Does Ciena Expect Of You

• Sense of urgency and accountability – what’s important to the customer is important to you; you make getting things done a priority.
• Problem solver – you possess the ability to analyze and methodically solve complex technical problems using engineering principles and approaches.
• Detail-oriented – you will deliver on objectives through meticulous, thorough, and comprehensive work.
• Commitment to learning – you keep abreast of technology developments and are keen to share your knowledge with others.

The Must Haves

• Minimum Bachelor’s degree in Electrical or Computer Engineering, Computer Science or other applicable scientific degree coupled with significant experience in the use of System Verilog, UVM, SVA, and simulators from major vendors.
• Proven ability in determining appropriate and comprehensive digital verification and coverage strategies

Assets

• DSP and/or Forward Error Correction
• Familiarity with programming languages such as: Python, Make, bash, object-oriented programming, C, C++.
• Experience with
• Formal verification methods
• Using Jira for bug tracking and GIT for source code management and revision tracking

At Ciena, we are committed to building and fostering an environment in which our employees feel respected, valued, and heard. Ciena values the diversity of its workforce and respects its employees as individuals. We do not tolerate any form of discrimination.
If contacted in relation to a job opportunity, please advise Ciena of any accommodation measures you may require.