Senior Engineer I-Analog Design

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The Timing and Communication Group (TCG) at Microchip is actively seeking an analog design engineer. The responsibility spans wide range of activities such as the design, simulation and validation of analog integrated circuits (ICs). The products are usually mixed signal SOC designs.
The Analog team develops the critical IP blocks used in the TCG timing products. These circuits include multi-GHz PLL circuits, high speed digital circuits, MEMS drivers and high-speed performance IO pads.
As an Analog Design Engineer and as part of the Analog IP team the individual will:

• Simulate analog circuits across process corners and operating conditions
• Work with analog design lead and architects to design specific analog IP blocks
• Models design blocks to be included on top level mixed signal simulations
• Block level validation of process silicon devices and system level lab evaluation

Requirements/Qualifications

• 2-years minimum industrial experience
• Strong knowledge in Cadence IC design flow and tools
• Knowledge in scripting and automation using SKILL language, Python, Perl and TCL is a plus
• Strong knowledgeable in Verilog-A for analog behavioral modeling and simulation
• Good communication, teamwork skills and experience working with multi-site team desirable
• Perform analog/mixed signal circuit design and design verification using deep submicron CMOS process technology
• Experience in simulation and verification of mixed signal designs in geometries in CMOS 0.13um, 40nm, 28nm and smaller CMOS geometries is desired
• Bachelor's or master’s degree in Electrical Engineering

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