Software Engineer ( Hardware & Networking)

Astreya is a leading IT solutions provider to deliver technology-enabled services and fuel digital transformation to some of the most exciting companies on the planet. We are working with the world's most recognisable and innovative organisations through co-creating scalable solutions with fast-moving teams. Here you will have the creative autonomy to build new capabilities for next generation hardware architectures. You will get exposure to a wide variety of new tools and technologies to improve ASIC design verification. By joining the verification engineering team you will witness advances in continuous technical innovation and showcase the team’s successes as well as facilitate continuous career development. We are seeking for professional with 5+ experience in the following:

Key Responsibilities:

• Debug test failures to determine the root cause; work with RTL engineers to resolve design defects and correct any test issues
• Propose innovative ways to architect reusable test-benches
• Offer mentorship to junior engineers
• Estimate the time required to write the new feature tests and any required changes to the test environment
• Push for adoption of best practices in the industry
• Drive the test-bench architecture and development of leading edge IP
• Develop directed and constrained random test scenarios as identified in the test plan
• Evaluate tools for improving performance and reduce the development cycle
• Build test plan documentation, accounting for interactions with other features, with focus on use cases described in the architecture and design specifications
• Review functional and code coverage metrics – modify or add tests or constraint random tests to meet the coverage requirements
• Collaborate with design engineers to understand the new features to be verified

Qualifications / Experience:

• Proficient working in Linux and Windows environments
• Experience and knowledge with IEEE security protocols (such as MACsec, IPsec)
• Expert level analytical and problem-solving skills with a willingness to learn and the capability to take on complex problems.
• Hands-on experience with UVM based verification frameworks and test-benches, processes and flows
• Scripting language experience: Perl, Ruby, Makefile, shell preferred.
• Proficient in IP level ASIC verification
• Extensive experience in designing and implementing self-checking test-benches, coverage closure techniques and regression management flows
• Experience and knowledge of communications standards (such as Ethernet, Flex Ethernet, OTN, Interlaken)
• Good working knowledge of SystemC and TLM with some related experience.
• Strong team player with excellent communication skills and experience collaborating with other engineers located in different sites/timezones.
• Experienced with Verilog, System Verilog, C, and C++
• Proficient in debugging RTL code using simulation tools
• Exposure to simulation profile, efficiency improvement, acceleration, HLS tools/process
• Bachelors or Masters degree in computer engineering/Electrical Engineering/computer systems/computer science
• Exposure to leadership or mentorship opportunities

Physical Demand & Work Environment:

• Must be able to use a computer
• Must have the ability to communicate effectively
• Must have the ability to perform office-related tasks which may include prolonged sitting or standing
• Some positions may require occasional repetitive motion or movements of the wrists, hands, and/or fingers
• Must have the ability to move from place to place within an office environment