Asic Design Verification Engineer

Jarvis is currently working with a leading semiconductor platform seeking a skilled and dedicated Digital ASIC Design Verification Engineer to join the dynamic team in Montreal. As a design verification engineer, you will play a crucial role in ensuring the quality and reliability of our digital ASIC designs through comprehensive verification methodologies.

Responsibilities:

• Write and maintain testbenches: Design and develop efficient and reusable testbenches using SystemVerilog and UVM (Universal Verification Methodology) to thoroughly verify complex digital designs.
• Create and execute test plans: Collaborate closely with design and architecture teams to develop detailed test plans, write test cases, and execute them to ensure functional correctness and performance compliance.
• Develop and execute verification strategies: Define and implement comprehensive verification plans and methodologies to validate the functionality and performance of digital ASIC designs.
• Debug and resolve issues: Identify and debug design and verification issues using industry-standard tools and techniques, working closely with cross-functional teams to achieve timely resolutions.

Requirements:

• ASIC/SoC experience: Possess 5-10 years of hands-on experience in digital ASIC/SoC design and verification, with a strong understanding of the overall design flow.
• Strong verification methodology background: Thorough understanding of advanced verification methodologies, including constrained-random testing, coverage-driven verification, and assertion-based verification.
• Education: Hold a Master's or PhD degree in Electrical Engineering or equivalent, with a specialization in digital design or verification.
• Proficiency in SystemVerilog and UVM: Solid knowledge and experience in developing testbenches and test cases using SystemVerilog and UVM, with the ability to write reusable and scalable verification components.

Salary is up to $175K CAD plus full benefits!