Engineer I/Ii - Emulation

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The Architecture Co-Verification team (ACOV) is an exciting, fast-paced team responsible for enabling HW/FW development and co-verification of state-of-art System-On-Chip (SoC) devices using industry-leading HW emulators (such as Cadence Palladium) and FPGA based prototyping platforms (such as Cadence Protium). The team is deployed in all aspects of SoC development phases from architectural exploration to post-silicon validation, HW/FW co-development, pre-silicon functional co-verification, pre/post-silicon performance testing, power analysis, and critical post-silicon investigations. As an emulation Engineer, you will be working closely with architects, hardware designers, firmware engineers, and verification teams throughout the SoC development process.
This is a role for a versatile engineer that enjoys the challenges of HW/FW co-development and system-level co-verification using leading-edge HW emulators and FPGA platforms. It’s a high-visibility role that will develop a wide range of skills and exceptional problem-solving abilities.
Responsibilities could include but are not limited to the following:

• Developing FW and tests for pre-silicon subsystem/system level co-verification
• Troubleshoot and resolve complex problems in embedded multi-core real-time systems executing emulation test plans
• Utilize state of the art protocol analyzers for analysis and error injection
• Utilization of test and defect tracking tools to document and report on verification progress and product quality
• Effectively present technical information to small teams of engineers
• Porting SoC RTL to industry leading HW emulators and FPGA platforms
• Developing common test ecosystem across pre/post silicon
• Developing emulation specific HW for pre-silicon subsystem/system level co-verification

Requirements/Qualifications

• Willing to learn in a fast-paced environment, and being an organized self-starter
• Proficient Linux experience and strong programming/scripting skills with languages such as C, Python, Tcl and Bash
• Proficient in digital design, RTL coding with VHDL, Verilog, or System Verilog experience
• Creation & management of system validation testing schedules and their execution
• Experience with one or more serial protocols such as SAS/SATA/NVMe/ PCIe is considered an asset
• BS/MS degree or higher in Electrical/Electronic Engineering or Computer Engineering
• 0 - 2+ years of relevant work experience
• Knowledge of key components of a server and storage solution including Windows/Linux host driver architectures

Desired Skills

• Excellent analytical and documentation skills
• Strong problem solving, communication and interpersonal skills are required

Travel Time
0% - 25%