Design Verification Engineer Jobs

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The Role
This is an exciting opportunity to work in the AMD PCIe IP Verification Team as Senior Verification Engineer. The candidate will have an opportunity to work on state-of-the-art verification environment using UVM verification methodology. We are looking for dynamic candidates with excellent communication skills. The role also provides opportunity to work on various aspects of verification such as performance verification, power aware verification besides functional verification.
The Person
We are looking for a dynamic candidate who will have great opportunity to work on the state-of-the-art products with leading verification methodology. Take your current verification expertise and apply that to state of the are data center products involving complex protocols like PCIE, CXL, networking etc. We are looking for team players with good communication skills.
Key Responsibilities

• Work with designers to get coverage closure
• Create block level verification plan, test plans and full chip test plan
• Integrate VIPs as needed
• Develop block level test bench and tests in UVM methodology including scoreboard
• Work on a new UVM based PCIe transaction Layer test-bench

Preferred Experience

• Execution of test plan, debugging failures, write functional coverage objects and review the code coverage and functional coverage with design team
• Good problem-solving skills and analytical ability
• Prior experience in architecting and developing self-checking constrained random verification environment using System Verilog and UVM verification methodology
• Excellent communication skills
• Prior experience with PCIE Protocol
• Familiarity with EDA tools for simulation, debugging, coverage analysis
• Programming in scripting languages like Python, TCL and Perl
• Prior experience with protocols such as AXI, APB, AHB etc.
• Good understanding of object-oriented programming concepts
• Prior experience in verifying is system/sub system level involving multiple blocks

Desirable Qualifications

• Prior experience in bringing up gate level simulation and debugging issues
• Prior experience with verifying PCIE IP
• Prior experience in integrating Verification IPs (VIP) & UVC in verification environment
• Exposure to formal verification methodologies
• System level understanding of PCIE based systems

Academic Credentials

• Master's Degree in Electrical Engineering/Computer Engineering/related equivalent Or
• PhD in Electrical Engineering or Computer Engineering or related equivalent with Or
• Bachelor's Degree in Electrical Engineering/Computer Engineering/related equivalent

LOCATION:Markham/ Ottawa/ Vancouver/ Calgary
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.